What is JTAG ?
JTAG (Joint Test Action Group, Joint Test Action Group) is an international standard test protocol, which is mainly used for internal chip testing and system simulation and debugging. JTAG technology is an embedded debugging technology, which encapsulates a special test circuit TAP (Test Access Port, test access port) inside the chip, and tests the internal nodes through a special JTAG test tool.
Most of the more complex devices today support the JTAG protocol, such as ARM , DSP, FPGA devices, and so on. The standard JTAG interface is 4 wires: TMS, TCK, TDI, TDO, which are respectively test mode selection, test clock, test data input and test data output.
What is the role of JTAG ?
Main use: chip internal testing, debugging.
JTAG was originally used to test the chip. The basic principle of JTAG is to define a TAP (Test Access Port, test access port) inside the device to test the internal nodes through a dedicated JTAG test tool . JTAG testing allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, which enables separate testing of each device. Today, the JTAG interface is also commonly used to implement ISP (In-System Programmer, in-system programming) and program devices such as FLASH.
The TAG programming method is online programming. In the traditional production process, the chip is pre-programmed and then mounted on the board. The simplified process is to fix the device to the circuit board first, and then use JTAG programming, which greatly speeds up the project progress. The JTAG interface can program all the components inside the DSP chip.
A CPU with a JTAG Debug interface module, as long as the clock is normal, can access the internal registers of the CPU and devices hung on the CPU bus through the JTAG interface, such as FLASH, RAM, SOC (such as 4510B, 44Box, AT91M series) built-in modules Registers, like UART, Timers, GPIO, etc.
The above are only the capabilities of the JTAG interface. To use these functions, the cooperation of the software is also required, and the specific functions are determined by the specific software.
Hardware Basics of JTAG
JTAG is implemented in hardware.
In the periphery of the cpu (note: the cpu here refers to the operation processing unit, which only includes the internal registers and basic components such as the operation unit), the processor (ie, the cpu expansion chip, not the soc) contains the hardware implementation of JTAG, and communicates with the outside world. Provide an interface.
Inside JTAG there is a state machine called the TAP controller. The state machine of the TAP controller changes the state through TCK and TMS, and realizes the input of data and instructions.
The standard JTAG interface is four wires (and optional):
TMS (mandatory) – mode selection , TMS is used to set the JTAG port in a specific test mode, and the TMS signal is valid on the rising edge of TCK. TMS is mandatory in the IEEE1149.1 standard. The TMS signal is used to control the transitions of the TAP state machine. Through the TMS signal, the TAP can be controlled to switch between different states.
TCK (mandatory) – clock, TCK is mandatory in the IEEE1149.1 standard. TCK provides an independent, basic clock signal for the operation of TAP, and all operations of TAP are driven by this clock signal.
TDI (mandatory) – data input , data is input to the JTAG port through TDI, TDI is mandatory in the IEEE1149.1 standard. TDI is the interface for data input. All data to be input to a specific register is serially input bit by bit through the TDI interface (driven by TCK).
TDO (mandatory requirement) – data output , data is output from the JTAG port through TDO, TDO is mandatory in the IEEE1149.1 standard. TDO is the interface for data output. All data to be output from a specific register is serially output bit by bit through the TDO interface (driven by TCK).
TRST (optional pin) – Test reset , input pin, active low.
This signal interface is optional in the IEEE 1149.1 standard, not mandatory. TRST can be used to reset (initialize) the TAPController. Because TAP Controll can also be reset (initialized) through TMS. So there are four-wire JTAG and five-wire JTAG points.
In addition to the above standard JTAG lines, there are other pins on the hardware JTAG interface, which are introduced together:
VTREF (mandatory) – The interface signal level reference voltage is normally connected directly to Vsupply. This can be used to determine the logic level used by the ARM’s JTAG interface (like 3.3V or 5.0V?)
RTCK (optional pin ) – Return Test Clock , used to synchronize the TCK signal. The clock signal fed back to the simulator by the target terminal is used to synchronize the generation of the TCK signal, and is directly grounded when not in use.
nSRST (optional pin ) – System Reset , resets the target system. It is connected with the system reset signal on the target board, and can reset the target system directly. At the same time, the reset condition of the target system can be detected. In order to prevent false triggering, an appropriate pull-up resistor should be added to the target end.
USER IN – User defined input . It can be connected to an IO to accept the control of the host computer .
USER OUT – User-defined output . It can be connected to an IO to feed back a state to the upper computer.
JTAG interface connection standard
Nowadays, there are two standards for the connection of JTAG interface, namely 14-pin interface and 20-pin interface, which are defined as follows.
Why are there multiple interface standards? Also, JTAG debugging can be realized with only standard 4/5 wires. Why does the actual interface have 20 pins/14 pins?
Since JTAG often uses flat cable connections, in order to enhance the anti-interference ability, this 20-pin interface appears by adding a ground wire between each signal line. But in fact, RTCK, USER IN, USER OUT are generally not used, so there is a 14-pin interface. For practical development and application, due to the stable power supply in the laboratory, the electromagnetic environment is good, and the interference is not large.
Note: The picture shows the interface circuit of various JTAG.
The JTAG hardware pins corresponding to 14 pins are described as follows:
The JTAG hardware pins corresponding to 20 pins are described as follows: